The subject matter discussed the background section should not be assumed to be prior art merely as a result of its mention in the background section. Similarly, a problem mentioned in the background section or associated with the subject matter of the background section should not be assumed to have been previously recognized in the prior art. The subject matter in the background section merely represents different approaches, which in and of themselves may also correspond to implementations of the claimed inventions.
The technology disclosed relates to testing internet traffic flows. In particular, it relates to reducing clock speed requirements for memory that stores statistics from testing with a data feed containing a multiplicity of streams.
When testing network traffic and network equipment, statistics about each of the streams, such as frame and byte counts, are counted and stored in memory. Smaller and faster cache memory or register memory may be suitable to keep track of the counters at high bandwidth rates. However, at 400 gigabit Ethernet (400 GbE), Terabit Ethernet (1 TbE), or higher data rates, thousands of streams may be tracked and analyzed, such that the volume of statistics render cache memory or register memory unsuitable, and RAMs suitable.
Although RAMs are suitable from the aspect of data volume, RAMs are not ideal from the aspect of speed. To update a statistic in a RAM, the data must be read from the RAM, modified, and then written back into the RAM. The maximum update rate is determined by the RAM read and write access times and the time to modify the data. In a simple RAM update, the maximum update rate is 1/(RAM read access time+time to modify the data+RAM write access time).
Tracking stream-based counters is straightforward when the maximum update time of RAM is fast enough to keep pace with the maximum frame rate. However, tracking stream-based counters is difficult when the maximum update time of RAM is too slow. Moreover, tracking stream-based counters is especially demanding because such statistics require the processing to be done in strict frame order.
At 400GbE data rates, the maximum frame rate is 400GbE/(8 bits*(12 byte inter-frame gap+8 byte preamble+64 byte frame)), which is over 595 million frames per second. Finding RAMs that can support reading-modifying-writing a counter at 595 million frames a second is quite difficult, especially if strict ordering is required. For example on the latest Xilinx FPGAs, True Dual Port Block RAMs have a maximum frequency of 525 Mhz and 585 MHz at the lower speed grades. Although the costliest and fastest FPGAs are claimed to run at 660 MHz, such FPGAs require pipeline delays on the read path at such speeds, thus requiring extra processing to handle ordering, as well as the update and write back to the other port of the dual port RAM. Circuitry running at such speeds will have difficulties to meet timing requirements, and limit the complexity of the types of statistics that can be supported.
An opportunity arises to provide a method and apparatus to process frames for stream statistics quickly enough with RAMs that have a maximum update time that is too slow to keep pace with the maximum frame rate of a data feed.